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type package tle 4473 gv53 pg-dso-12 tle 4473 gv52 pg-dso-12 dual low drop voltage regulator tle 4473 gv53 tle 4473 gv52 data sheet 1 rev. 1.1, 2008-09-19 features ? output 1: 300 ma, 3.3 v ( 3%) or 2.6 v ( 3%) output 2: 180 ma, 5 v ( 2%) low quiescent current consumption disable function separat ely for both outputs wide operation range: up to 42 v very low dropout voltage 2 independent reset circuits watchdog output protected against short circuit wide temperature range: -40 c to 150 c overtemperature protection overload protection functional description the tle 4473 is a monolithic integrated voltage regulato r with two very low-drop outputs, q1 for loads up to 300 ma and q2 providing a maximum of 180 ma. an input voltage in the range of 5.6 v v i 45 v is transformed to v q2 = 5.0 v ( 2%) and v q1 =3.3v 3% (tle 4473 gv53) or v q1 = 2.6 v 3% (tle 4473 gv52). the device is also available with dual 5 v output voltage, please refer to the tle 4473 gv55 data sheet. two inhibit pins al low a flexible power mana gement. both outputs can independently be enab led or disabled. thus the current consumption of the application can be reduced to a minimum. the quiescent current of th e tle 4473 with both outputs disabled is < 1 a. the tle 4473 is designed to supply microprocessor systems and sensors under the severe co nditions of automot ive applications and is therefore equipped with additional protection functions against overl oad, short circuit and overtemperature. the device operates in the wide junction te mperature range of -40 c to 150 c.
data sheet 2 rev. 1.1, 2008-09-19 tle 4473 gv53 tle 4473 gv52 the low drop regulator features a reset with adjustable power on delay for each of the outputs. in addition the outp ut for the microcontroller su pply comes up with a watchdog in order to supervise a microcontroller. figure 1 block diagram with typical external components aeb03507.vsd tle 4473 gv53 / tle 4473 gv52 reset generator reset generator watchdog current and saturation control, overcurrent protection overtemperature shutdown bandgap reference inhibit current and saturation control, overcurrent protection inhibit 10 f 4.7 k ? 4 2 q2 ro2 e. g. c i/o or sensor supply 100 nf 10 d2 3 ro1 5 q1 22 f or 10 f c core supply c reset 100 nf 11 d1 gnd 6, 12 4.7 k ? ignition c v bat inh2 9 i 7 inh1 8 ?1 1 wi watchdog (from c)
tle 4473 gv53 tle 4473 gv52 data sheet 3 rev. 1.1, 2008-09-19 reset and watchdog behaviour: the reset output ro1 is in high-state if the voltage on the delay capacitor c d1 is greater or equal v dl1 . the delay capacitor c d1 is charged with the current i dc1 for output voltages greater than the reset threshold v rt1 . if the output vo ltage drops below v rt1 (?reset condition?), the delay capacitor c d1 will be dischar ged rapidly. if v d1 reaches v dl1 , the reset output ro1 is set to low. at power-on, the charging process of c d1 starts from 0 v, whic h leads to the equation (1) for the power-on re set delay time. when the voltage at the delay capaci tor has reached v du1 and ro1 was se t to high, the watchdog circuit is e nabled and discharges c d1 with the constant current i dd1 . if there is no rising edge obse rved at the watchdog input, c d1 will be discharged down to v dl1 , where the reset output ro 1 will be set to low and c d1 will be charged again with the current i dc1 until v d1 reaches v du1 and reset will be set high again. if a watchdog pulse (rising edge at watchdog input wi) occurs during the discharge period, c d1 is charged again and the re set output stays high. after v d1 has reached v du1 , the periodical cycle starts again. the watchdog timing is shown in figure 2 . the maximum duration between two watchdog pulses corresponds to th e minimum watchdog trigger time t wi,tr . higher capacitances on pin d1 result in larger watchdog trigger time: (2) if the output voltage q2 decreases below v rt2 , the external capacitor c d2 is discharged. when the voltage at this capacitor drops below v dl2 , a reset signal is generated at pin 11 (ro2), i.e. the reset outpu t is set to low-level. if th e output voltage rises above the reset threshold, c d2 will be charged with the constant current i dc2 . after the power-on- reset time, the vo ltage at the capacitor reaches v du2 and the reset outp ut will be set to high again. the value of the power-on-reset time can be set within a wide range depending of th e capacitance of c d2 using equation (1) analogous for q2. t don , c d1 v du1 i dc1 ---------------------------- - = t wi,tr max 0.42 ms/nf c d1 =
data sheet 4 rev. 1.1, 2008-09-19 tle 4473 gv53 tle 4473 gv52 figure 2 watchdog timing schedule aed03099_4473gv53 w v v v q d1 v v wo v du1 - v dl1 () ( dc1 + dd1 ) dc1 x dd1 t wd, p = wd, l t wd, p t wi, tr t wd, l t = v v ( du1 - dl1 ) dc1 t = v v ( du1 - dl1 ) dd1 du1 v v dl1 wi, tr c d1 ; ; d1 c d1 c t t t t t
tle 4473 gv53 tle 4473 gv52 data sheet 5 rev. 1.1, 2008-09-19 figure 3 pin configuration tle 4473 gv53, tle 4473 gv52 (top view) table 1 pin definitions and funct ions (tle 4473 gv53, tle 4473 gv52) pin no. symbol function 1wi watchdog input; input for watchdog pul ses, positive edge triggered 2ro2 reset output for q2; open collector output 3ro1 reset and watchdog output for q1; open collector output 4q2 output voltage 2 (5 v); block to gnd with a capacitor c q2 22 f, esr < 5 ? at 10 khz or c q2 10 f, esr < 4 ? at 10 khz 5q1 output voltage 1 (3.3 v/2.6 v); block to gnd with a capacitor c q1 10 f, esr < 5 ? at 10 khz 6n.c. not connected; connect to gnd 7i input voltage; block to gnd directly at the ic with a ceramic capacitor. 8inh1 inhibit input 1; low level at inh2 and inh1 disables q2 and q1 9inh2 inhibit input 2; low level disables q2 10 d2 reset delay 2; connect a capacitor to set reset delay for q2 11 d1 reset delay 1; connect a capacitor to gnd to set reset delay and watchdog timing for q1 12 gnd ground heatsink n. c. not connected; connect to gnd pin 6 and heat slug should be connected to gnd p-dso-12-6 aep03318_4473gv53.vsd 1 wi 2 ro2 3 ro1 12 11 10 d1 d2 4 q2 5 q1 6 n.c. 9 8 7 inh2 inh1 i gnd
data sheet 6 rev. 1.1, 2008-09-19 tle 4473 gv53 tle 4473 gv52 table 2 absolute maximum ratings -40 c < t j < 150 c parameter symbol limit values unit remarks min. max. input i voltage v i -42 45 v ? current i i ? ? ma internally limited stand-by output q2 voltage v q2 -0.3 18 v ? current i q2 ? ? ma internally limited main output q1 voltage v q1 -0.3 18 v ? current i q1 ? ? ma internally limited inhibit input inh1 voltage v inh1 -42 45 v ? current i inh1 -2 2 ma ? inhibit input inh2 voltage v inh2 -42 45 v ? current i inh2 -2 2 ma ? reset output ro1 voltage v ro1 -0.3 18 v ? current i ro1 ? ? ma internally limited reset output ro2 voltage v ro2 -0.3 18 v ? current i ro2 ? ? ma internally limited reset delay d1 voltage v d1 -0.3 7 v ? current i d1 -5 5 ma ? reset delay d2 voltage v d -0.3 7 v ? current i d -5 5 ma ?
tle 4473 gv53 tle 4473 gv52 data sheet 7 rev. 1.1, 2008-09-19 note: maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. watchdog input wi voltage v radj -0.3 7 v ? current i radj -5 5 ma ? temperatures junction temperature t j -40 150 c? storage temperature t stg -50 150 c? esd protection electrostatic discharge voltage v esd ?2 2 kv human body model table 2 absolute maximum ratings (cont?d) -40 c < t j < 150 c parameter symbol limit values unit remarks min. max.
data sheet 8 rev. 1.1, 2008-09-19 tle 4473 gv53 tle 4473 gv52 note: in the operating range th e functions given in the circ uit description are fulfilled. integrated protection functions are design ed to prevent ic des truction under fault conditions. protection functions are no t designed for repe titive operation. table 3 operating range parameter symbol limit values unit remarks min. max. input voltage v i 5.6 42 v q1 & q2 4.5 42 v only q1 regulating junction temperature t j -40 150 c? thermal resistances pg-dso-12 junction pin r thj-pin ?3k/w? junction ambient r thj-a ? 115 k/w pcb heat sink area 0 mm 2 1) junction ambient r thj-a ? 100 k/w pcb heat sink area 100 mm 2 1) junction ambient r thj-a ? 60 k/w pcb heat sink area 300 mm 2 1) junction ambient r thj-a ? 48 k/w pcb heat sink area 600 mm 2 1) 1) package mounted on pcb 80 80 1.5 mm 3 ; 35 cu; 5 sn; zero airflow.
tle 4473 gv53 tle 4473 gv52 data sheet 9 rev. 1.1, 2008-09-19 electrical characteristics v i1 =13.5 v; v inh1 = v inh2 = 5v; ? 40 c < t j < 150 c; unless otherwise specified parameter symbol limit valu es unit test condition min. typ. max. regulator 2: output q2 output voltage v q2 4.90 5.0 5.10 v 1 ma < i q2 <180ma; 6v< v i <28v output current limitation i q2 200 300 600 ma v q2 =4.5v output drop voltage; v drq2 = v i 2 ? v q2 v drq2 ?300600mv i q2 = 100 ma; 1) load regulation ? v q2,lo ?15 50mv1ma< i q2 < 200 ma; line regulation ? v q2,li ?5 20mv i q2 = 1 ma; 6v< v i <28v power supply ripple rejection psrr ?65 ?db f r = 100 hz; v r = 1 v pp current consumption quiescent current; stand-by i q = i i ? i q2 i q ?165 a tle 4473 gv52; i q2 = 500 a; t j = 25 c; v inh1 < v inh1 off (q1 off) ?205 a tle 4473 gv52; i q2 = 500 a; t j = 85 c; v inh1 < v inh1 off (q1 off) ?180 a tle 4473 gv53; i q2 = 500 a; t j = 25 c; v inh1 < v inh1 off (q1 off) ?210 a tle 4473 gv53; i q2 = 500 a; t j = 85 c; v inh1 < v inh1 off (q1 off) ?235a i q2 = 500 a; v inh1 < v inh1 off (q1 off)
data sheet 10 rev. 1.1, 2008-09-19 tle 4473 gv53 tle 4473 gv52 current consumption (cont?d) quiescent current; stand-by i q = i i ? i q2 i q 5ma i q2 = 100 ma; v inh1 < v inh1 off (q1 off) quiescent current; inhibited i q ??1 av inh1 =v inh2 = 0v; t j <85c inhibit input inh2 turn-on voltage v inh2 on ??2.3vv q2 on turn-off voltage v inh2 off 0.8 ? ? v v q2 off h-input current i inh2 on ?1 0.5 3 a v inh2 =5v l-input current i inh2 off ?1 0.1 1 a 0v< v inh2 <0.8v reset timing d2 charge current i dc2 5.0 9.0 13.0 a v d2 = 0.7 v upper timing threshold v du2 1.6 1.8 2.2 v ? lower timing threshold v dl2 0.3 0.45 0.6 v ? saturation voltage v d2,sat 100 mv v q2 < v rt2 reset delay time t rd2 12 20 28 ms c d2 = 100 nf reset reaction time t rr ?10 s c d2 = 100 nf electrical characteristics (cont?d) v i1 =13.5 v; v inh1 = v inh2 = 5v; ? 40 c < t j < 150 c; unless otherwise specified parameter symbol limit valu es unit test condition min. typ. max.
tle 4473 gv53 tle 4473 gv52 data sheet 11 rev. 1.1, 2008-09-19 reset output ro2 reset switching threshold v rt2 4.5 4.65 4.8 v ? reset output current i ro2 ? ? 1.4 ma collector current of ro1, power good, reset still delayed. v q2 =5v, v d2 =0v,v ro2 =0.3v reset output low voltage v ro2l ? 0.15 0.3 v v q2 1 v, v d2 =0v, i ro2 = 0.5ma reset high voltage v ro2h 4.5 ? ? v r ro2,ext =4.7k ? regulator 1: output q1 output voltage v q12 3.20 3.3 3.40 v tle 4473 gv53 1ma< i q1 <300ma; 4.5 v < v i <28v output voltage v q12 2.52 2.60 2.68 v tle 4473 gv52 1ma< i q1 <300ma; 4.5 v < v i <28v output current limitation i q1 350 500 600 ma v q1 =3.0v (tle 4473 gv53); v q1 =2.3v (tle 4473 gv52) load regulation ? v q1,lo ?5 50mv5ma< i q1 < 3 00 ma; line regulation ? v q1,li ?5 20mv i q1 = 5 ma; 6v< v i <28v power-supply- ripple-rejection psrr ?65 ?db f r = 100 hz; v r = 1v pp electrical characteristics (cont?d) v i1 =13.5 v; v inh1 = v inh2 = 5v; ? 40 c < t j < 150 c; unless otherwise specified parameter symbol limit valu es unit test condition min. typ. max.
data sheet 12 rev. 1.1, 2008-09-19 tle 4473 gv53 tle 4473 gv52 current consumption quiescent current; i q = i i ? i q1 ? i q2 i q ?200265a tle 4473 gv52; i q1 = 500 a; q1 on; q2 off; t j < 85c ?210280a tle 4473 gv53; i q1 = 500 a; q1 on; q2 off; t j < 85c ?720ma i q1 = 300 ma i q2 = 500 a, v q1 & v q2 on ?250500a i q2 = i q1 = 500 a; v q1 & v q2 on inhibit input inh1 turn-on voltage v inh1 on ??2.3vv q1 on turn-off voltage v inh1 off 0.8 ? ? v v q1 off h-input current i inh1 on ?1 0.5 3 a v inh1 =5v l-input current i inh1 off ?1 0.1 1 a 0v< v inh1 <0.8v watchdog and reset timing d1 charge current i dc1 3.0 7.0 11.0 a v d1 = 0.7 v discharge current i dd1 1.1 1.5 3.7 a v d1 = 0.7 v upper timing threshold v du1 0.7 1.1 1.6 v ? lower timing threshold v dl1 0.2 0.35 0.6 v ? electrical characteristics (cont?d) v i1 =13.5 v; v inh1 = v inh2 = 5v; ? 40 c < t j < 150 c; unless otherwise specified parameter symbol limit valu es unit test condition min. typ. max.
tle 4473 gv53 tle 4473 gv52 data sheet 13 rev. 1.1, 2008-09-19 watchdog and reset timing d1 (cont?d) saturation voltage v d1,sat 100 mv v q1 < v rt2 watchdog trigger time t wi,tr 24 32 40 ms c d1 = 100 nf reset delay time t rd1 11 17 23 ms c d1 = 100 nf reset reaction time t rr ?5.0 s c d1 = 100 nf reset output ro1 reset switching threshold v rt1 2.97 3.08 3.18 v tle 4473 gv53 2.34 2.42 2.50 v tle 4473 gv52 reset threshold headroom v r1head 100 ? ? mv tle 4473 gv53 reset threshold headroom v r1head 80 ? ? mv tle 4473 gv52 reset output current i ro1 ? ? 1.4 ma collector current of ro1, power good, reset still delayed. v q1 =3.30v (tle 4473 gv53), v q1 =2.60v (tle 4473 gv52); v q2 =5.0 v; v d1 =0 v,v ro1 =0.3 v reset output low voltage v ro1l ?0.10.3v v q1 1 v, v d1 =0v, i ro1 =0.5ma reset output high voltage v ro1h 2.45 ? ? v r ro1,ext =4.7k ? connected to q1;tle 4473 gv52 reset output high voltage v ro1h 3.15 ? ? v r ro1,ext =4.7k ? connected to q1;tle 4473 gv53 1) drop voltage = v i ? v q (measured when the output voltage has dropped 100 mv from the nominal value obtained at 13.5 v input) electrical characteristics (cont?d) v i1 =13.5 v; v inh1 = v inh2 = 5v; ? 40 c < t j < 150 c; unless otherwise specified parameter symbol limit valu es unit test condition min. typ. max.
data sheet 14 rev. 1.1, 2008-09-19 tle 4473 gv53 tle 4473 gv52 package outlines figure 4 pg-dso-12 (plastic dual small outline) green product (rohs compliant) to meet the world-wi de customer requirements for envi ronmentally friendly products and to be compliant with government regula tions the device is available as a green product. green products are rohs-compliant (i.e pb-free finish on le ads and suitable for pb-free soldering according to ipc/jedec j-std-020). 2.35 0.1 1) does not include plastic or metal protrusion of 0.15 max. per side (heatslug) standoff index marking 1 12 2.6 max. 7.8 0 +0.1 6 7 6 1 7 12 0.8 0.1 (1.55) 0.25 5? 3? heatslug 10.3 0.3 0.25 b 7.5 0.1 1) b +0.075 -0.035 0.7 0.15 a 6.4 0.1 1) +0.13 0.4 0.25 m a c b 12x 0.1 1.6 0.1 4.2 5.1 0.1 1 bottom view seating plane 12x 0.1 c c (0.2) 0.1 standout 0.05 5 x 1 = 5 0.1 pg-dso-12-4, -5, -8, -11, -12, -16-po v04
tle 4473 gv53 tle 4473 gv52 data sheet 15 rev. 1.1, 2008-09-19 revision history version date changes rev. 1.1 2008-19-09 initial version of ro hs-compliant derivate of tle 4473 gv53 page 1 : aec certified statement added page 1 and page 14 : rohs compliance statement and green product feature added page 1 and page 14 : package changed to rohs compliant version legal disclaimer updated rev. 1.0 2004-07-14 initial version you can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products . dimensions in mm smd = surface mounted device
edition 2008-09-19 published by infineon technologies ag 81726 mnchen, germany ? infineon technologies ag 2008. all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hints give n herein, any typical values stated herein and/or any information regarding the application of the devi ce, infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms an d conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or system s with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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